Transistors are commonly used in the integrated circuits (ICs). Current ground rules, for example, below 90 nm, require higher carrier mobility. To improve carrier mobility (e.g., electrons or holes), strain engineering has been applied. Generally, inducing a tensile strain in the channel of n-type transistors improves electron mobility while a compressive strain in the channel of p-type transistors improves hole mobility. Various techniques have been proposed to induce the desired stress in the channel region of transistors. One technique includes forming stressors in source/drain regions of a transistor. Other techniques include, for example, providing the desired stress inducing material in the shallow trench isolations (STIs) or over the transistors as etch stop liners (ESLs).
However, we have discovered that conventional integration schemes applying stress engineering is ineffective. For example, current integration schemes counter the effect of the stress inducing materials, such as relaxing the stress being applied. This can undesirably affect transistor performance.
In view of the foregoing, it is desirable to provide effective stress inducement to improve transistor performance.